The advisors of this laboratory are Dr. Chu Yu and Dr. Meng-Hsueh Chiang. So far the graduate members in this lab have 7 persons, in addition to many B.S. students. This space size of the laboratory holds about 50m2. Main laboratory equipment contains SUN workstation and IBM PC. EDA softwares in study include Cadence Tools¡BAvant! Tools¡BSynopsys Tools¡BHSPICE¡BMENTOR Tools, etc.
Dr. Chu Yu
Chu Yu received the B.S. and M.S. degrees in electronic engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 1991 and 1993, respectively, and the Ph.D. degree in electrical engineering from the National Taiwan University, Taipei, Taiwan, in 1999.
Since 2000, he has been a member of the faculty in the Department of Electronic Engineering, National I-Lan University, where he is currently an associate professor. His research interests include the design of ASIC architectures and speech/image coding.
Recently, our studies are in many aspects, as follows:
1. The wavelet transform, similar to the Short-Time Fourier Transform, furnishes an alternative approach to signal processing, especially suitable for the analysis of spatial and spectral locality. However, the 2-D wavelet transform needs the same enormous computation as their counterpart Fourier transforms. In this paper, we present a low-cost VLSI architecture for 2-D biorthogonal discrete wavelet transforms. Both the efficient arrangement of a computation schedule and the symmetric property of biorthogonal filters used in this architecture contribute to the hardware cost minimization. For the computation of an N ´ N 2-D image with a filter length L, this architecture spends near N2clock cycles, and requires about 2NL - 2N storage unit, 15L/8 multipliers for even-length filters or 15ëL/2+1û /4 multipliers for odd-length filters, as well as 4(L-1) adders.
Fig1. 2-D DWT ASIC architecture
2. This paper presents an ASIC architecture for embedded block coding with optimized truncation (EBCOT) in JPEG 2000, which is compatible with the entropy coder defined in ISO/IEC 155444-1. The proposed architecture employs a parallel-based approach to speed up EBCOT coding with non-stripe-causal mode. Therefore, a column of samples (4 bits) is encoded at a single clock cycle. This result will effectively shorten the computation time of EBCOT coding, and reduce data memory accesses. For an n¡Ñn code block and r bit-planes, the proposed architecture only spends 0.25 rn2 clock cycles, under an acceptable area overhead.
Fig. 2. EBCOT ASIC architecture
3. This paper presents an area-efficient ASIC architecture for the context-based arithmetic encoder in JPEG2000, which is compatible with the arithmetic encoder defined in ISO/IEC 155444-1. The proposed architecture employs the look-ahead computation and the analysis of data dependency to improve the performance of arithmetic encoding. Based on these two strategies, the average of encoding cycle time for each input symbol can be reduced significantly. According to our analysis and the simulation result, a byte of compressed data output for the proposed architecture spends only two clock cycles in most cases and at most five clock cycles in the worst case. In addition, we have successfully implemented the proposed architecture in an FPGA and have taken the validation of its function.
Fig. 3 MQ encoder for JPEG2000
4. In recent years digital speech processing techniques has made revolutionary advances. One of the techniques that lead to the improvement of voice-controlled toys, multimedia sound effects, and mobile as well as satellite phones is low-bit-rate speech coding. In this paper, we present an ASIC architecture for speech synthesis at 1.6 kbps. The processing algorithm is formulated from the viewpoint of hardware-oriented design. Based on the proposed speech synthesizer, the developed architecture consumes less hardware resources but still attains satisfactory quality. It is therefore suitable for hardware implementation.
Fig.4 1.6 kps speech decoder
Fig. 5 All-pole filter structure (LSF synthesis)
With the coming of multimedia era, image coding requires higher performance and newer features to meet various applications in the future. To satisfy these requirements, new still image coding has been developed, known as JPEG 2000. This new coding has also become an ISO/IEC international standard since 2000. Therefore, we will plan combining many previous works into a total solution of SOC chip in the future. These works includes 2-D Discrete Wavelet Transform, Embedded Block Coding with Optimized Truncation (EBCOT) coder, and MQ coder. The applications of the SOC Chip are addressed in digital photograph, color facsimile, printing, scanning, medical imagery, digital library, mobile applications, remote sensing, Internet, and E-commerce.
Dr. Meng-Hsueh Chiang
FIg. 1 cross-section of FD SOI and PD SOI devices